On Test Coverage of Path Delay Faults - VLSI Design, 1996. Proceedings., Ninth International Conference on

W e propose a coverage metric and a two-pass test generation method f o r path delay faults in combinational logic circuits. The coverage is measured f o r each line with a rising and a falling transition. However, the test criterion is different f r o m that of the slow-to-rise and slow-to-fall transition faults. The test, called “line delay test”, as a path delay test for the longest sensitizable path producing a given transition o n the target line. The max imum number of tests (and faults) is limited t o twice the number of lines. However, the line delay test criterion resembles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests f o r them. Fault simulation is used t o determine the coverage metric. For uncovered lines, an the second pass, several paths of decreasing length are targeted. W e present a theorem stating that a redundant stuck-at fault makes all path delay faults involving the faulty line untestable fo r either a rising or falling transit ion depending o n the type of the stuck-at fault. The use of this theorem considerably reduces the effort of delay test generation. W e give results o n benchmark circuits.